ADICLK=00, ADIV=00, ADLSMP=0, MODE=00, ADLPC=0
ADC configuration register 1
| ADICLK | Input clock select 0 (00): Bus clock. 1 (01): Bus clock divided by 2. 2 (10): Alternate clock (ALTCLK). 3 (11): Asynchronous clock (ADACK). |
| MODE | Conversion mode selection 0 (00): When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2’s complement output. 1 (01): When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion with 2’s complement output. 2 (10): When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion with 2’s complement output. 3 (11): When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2’s complement output . |
| ADLSMP | Sample time configuration 0 (0): Short sample time. 1 (1): Long sample time. |
| ADIV | Clock divide select 0 (00): The divide ratio is 1 and the clock rate is input clock. 1 (01): The divide ratio is 2 and the clock rate is (input clock)/2. 2 (10): The divide ratio is 4 and the clock rate is (input clock)/4. 3 (11): The divide ratio is 8 and the clock rate is (input clock)/8. |
| ADLPC | Low-power configuration 0 (0): Normal power configuration. 1 (1): Low power configuration. The power is reduced at the expense of maximum clock speed. |